Semiconductor memory device having output driver for high frequency operation

ABSTRACT

Provided is a semiconductor memory device having an output driver for high frequency operation. In the output driver of the semiconductor memory device, a first NMOS transistor and a second NMOS transistor are connected in series, the drain of the first NMOS transistor is connected to an output pad, and the source of the second NMOS transistor is connected to a ground voltage. In addition, a first internal voltage is applied to the gate of the first NMOS transistor, a second internal voltage is applied to a gate of the second NMOS transistor, and a voltage level of the second internal voltage is lower than the voltage level of an external supply voltage. The second internal voltage is generated directly from an internal voltage generating circuit of the semiconductor memory device or is externally applied. The voltage level of the second internal voltage is different from the level of an operating voltage of the semiconductor memory device.

BACKGROUND OF THE INVENTION

[0001] This application claims the priority of Korean Patent ApplicationNo. 2002-38890, filed on 5 Jul. 2002, in the Korean IntellectualProperty Office, the contents of which are incorporated herein in theirentirety by reference.

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory device,and more particularly, to a semiconductor device having an output drivercapable of preventing distortion of output data when the semiconductordevice performs a high frequency operation.

[0004] 2. Description of the Related Art

[0005] Presently, semiconductor memory devices must be highly integratedand capable of performing operations quickly. In line with this, a newlydeveloped memory that can transmit a considerable amount of data at ahigh speed while consuming low power is required. A double data ratedynamic random access memory (DDR DRAM) or a rambus DRAM having a higheroperating speed than a synchronous DRAM (SDRAM) having a maximumoperating speed of 100-200 MHz is expected to become popular.

[0006]FIG. 1 is a block diagram of a semiconductor memory device 100having a conventional output driver, and FIG. 2 is a waveform diagram ofan output wave of the output driver of FIG. 1.

[0007] Referring to FIG. 1, a semiconductor memory device 100 includesan output driver 110, a first driving circuit 120, and a second drivingcircuit 130. In the output driver 110, a first NMOS transistor N1 and asecond NMOS transistor N2 are connected in series. A drain of the firstNMOS transistor N1 is connected to an output pad DQ, and a source of thesecond NMOS transistor N2 is connected to a ground voltage VSS.

[0008] When data DATA is read, the first NMOS transistor N1 is turned onin response to a gate voltage VGATE. A gate Q of the second NMOStransistor N2 is turned on or off in response to a data voltage VEXTwhich is at the level of an external voltage EVCC.

[0009] The first driving circuit 120 receives a reference voltage REFVto generate the gate voltage VGATE. The second driving circuit 130receives data DATA and the external voltage EVCC to generate the datavoltage VEXT.

[0010] If data DATA is at a high level, the data voltage VEXT isgenerated at a high level, and thus the second NMOS transistor N2 isturned on. The output pad DQ outputs data DATA at a low level.

[0011] If data DATA is at a low level, the data voltage VEXT isgenerated at a low level, and thus the second NMOS transistor N2 isturned off. The output pad DQ outputs data DATA at a high level.

[0012] In general, the rambus DRAM has a high operating speed of 800Mbps. However, when the rambus DRAM operates at a high speed over 800Mbps, skew occurs in data DATA which is output to the output pad DQ.

[0013] A waveform of the gate voltage VEXT which is applied to the gateQ of the second NMOS transistor N2 is illustrated in FIG. 2(A).

[0014] Since the second NMOS transistor N2 is large in size, the load onthe gate Q is great, and thus the data voltage VEXT is not capable ofperforming a full swing. In particular, the data voltage VEXT is notcapable of performing the full swing more frequently when the datavoltage VEXT changes between the low level and the high level than whenthe data voltage VEXT continues at the high level.

[0015] As shown in FIG. 2(A), the swing of the data voltage VEXTdecreases by about 240 mV when the data voltage VEXT of the gate Qchanges between the low level and the high level in comparison to thecase in which the data voltage VEXT of the gate Q continues at the highlevel.

[0016] Due to the decrease in the swing as described above, a delay ofabout 57 ps for output of the output pad DQ occurs as shown in FIG.2(B). As a result, margin of setup time or hold time based on anexternal clock signal decreases in the output of the rambus DRAM.

[0017]FIG. 3 is a timing diagram showing the relationship between areference clock signal CTM of the rambus DRAM and data DATA. As a systemoperates at a high speed and a high operating frequency, a timespecification of output data becomes tight. The data DATA sensed from acell of the rambus DRAM is output such that its center is synchronizedwith a rising edge or a falling edge of the reference clock signal CTM.

[0018] The time from the rising edge or the falling edge of thereference clock signal CTM to the front of the data DATA is denoted asTQMAX, and the time from the rising edge or the falling edge of thereference clock signal CTM to the back of the data DATA is denoted asTQMIN. TQMAX and TQMIN are important specifications representing theoutput characteristics of the rambus DRAM.

[0019]FIG. 4 is a circuit diagram of an output driver circuit of therambus DRAM. FIG. 5 is a waveform diagram illustrating a read operationof the output driver circuit of FIG. 4. FIG. 6 is a timing diagramshowing a delay of data due to a rise in a voltage of a connection nodeof FIG. 4.

[0020] Referring FIG. 4, an output driver circuit 400 of the rambus DRAMincludes a driver portion 410 having NMOS transistors N1 and N2, whichare connected in series, an output pad DQ, and a precharge transistor420.

[0021] In FIG. 4, a termination voltage VTERM and a termination resistorRTERM outside of a chip (not shown) where the output driver circuit 400is mounted are shown.

[0022] Hereinafter, the operation of the output driver circuit 400 ofthe rambus DRAM will be described with reference to FIG. 4. When thedata DATA is read, a first gate voltage VGATE is applied to the gate ofthe first NMOS transistor N1 of the driver portion 410 to turn on thefirst NMOS transistor N1. The first gate voltage VGATE is lower than theoperating voltage of the device.

[0023] When the data DATA is not read, the first gate voltage VGATE isapplied to the first NMOS transistor N1, and the first NMOS transistorN1 is turned on. Therefore, the capacitance of the driver portion 410when the output pad DQ is viewed from outside increases, and thus asignal transmitted from another device may be distorted. Accordingly,the first gate voltage VGATE is required to be applied only when thedata DATA is read.

[0024] The data DATA sensed from a DRAM core is applied to the gate Q ofthe second NMOS transistor N2. If the data DATA applied to the gate Q ofthe second NMOS transistor N2 is at a high level, the second NMOStransistor N2 is turned on and the data DATA at a low level is outputthrough the output pad DQ.

[0025] The precharge transistor 420 precharges a connection node A ofthe first NMOS transistor N1 and the second NMOS transistor N2 to alevel of a threshold voltage of the first gate voltage VGATE of thefirst NMOS transistor N1, so as to prevent the first NMOS transistor N1from being turned on when the data DATA is not read.

[0026] Referring to FIG. 5, when the data DATA is read, the voltagelevel of the first gate voltage VGATE is raised from 0 V to the highlevel. The second gate voltage PVGATE, which is at a high level toprecharge the connection node A, falls to a low level.

[0027] When the first gate voltage VGATE is raised from the low level tothe high level, a charge coupling occurs in the connection node A due tothe gate of the first NMOS transistor N1 to junction overlap. Therefore,the voltage level of the connection node A is raised by 100 mV, as shownin FIG. 5.

[0028] The rise in the voltage level of the connection node A decreasesTQMAX by 13 ps when the data DATA is output to the output pad DQ at thehigh level.

[0029] If during a process the applied voltage, the temperature, or thelike of the device is changed and thus the raised voltage of theconnection node A increases, the delay in outputting first data at ahigh level through the output pad DQ will also increase.

SUMMARY OF THE INVENTION

[0030] The present invention provides a semiconductor memory devicehaving an output driver which is capable of outputting data at a highfrequency without distortion of data.

[0031] According to a first aspect of the present invention, there isprovided a semiconductor memory device having an output driver in whicha first NMOS transistor and a second NMOS transistor are connected inseries, a drain of the first NMOS transistor is connected to an outputpad, and the source of the second NMOS transistor is connected to aground voltage. In the semiconductor memory device, a first internalvoltage is applied to the gate of the first NMOS transistor and a secondinternal voltage is applied to the gate of the second NMOS transistor,and a voltage level of the second internal voltage is lower than thevoltage level of an external supply voltage.

[0032] In one embodiment, the second internal voltage is generateddirectly from an internal voltage generating circuit of thesemiconductor memory device or is externally applied from the outside.The voltage level of the second internal voltage can be different fromthe level of an operating voltage of the semiconductor memory device.

[0033] According to a second aspect of the present invention, there isprovided a semiconductor memory device having an output driver in whicha first NMOS transistor and a second NMOS transistor are connected inseries, the drain of the first NMOS transistor is connected to an outputpad, and the source of the second NMOS transistor is connected to aground voltage. The device includes a driving circuit which applies adriving voltage to the gate of the second NMOS transistor in response todata and an internal supply voltage. In the semiconductor memory device,a ground voltage level of the driving circuit is higher than the voltagelevel of the ground voltage to which the source of the second NMOStransistor is connected.

[0034] The voltage level of the driving voltage can be different fromthe level of an operating voltage of the semiconductor memory device.The voltage level of the driving voltage can be lower than the voltagelevel of an external supply voltage.

[0035] According to a third aspect of the present invention, there isprovided a semiconductor memory device having an output driver in whicha first NMOS transistor and a second NMOS transistor are connected inseries, the drain of the first NMOS transistor is connected to an outputpad, and the source of the second NMOS transistor is connected to aground voltage. The device includes a precharge transistor the source ofwhich is connected to a connection node of the first NMOS transistor andthe second NMOS transistor and the drain of which is connected to asupply voltage. In the semiconductor memory device, the prechargetransistor includes a voltage compensating circuit for lowering the risein the voltage level of the connection node due to the rise in thevoltage level of the gate of the first NMOS transistor.

[0036] The voltage compensating circuit can include a capacitor which isconnected between the gate and the source of the precharge transistor.The capacitor can have the same capacitance as a coupling capacitorbetween the gate and the source of the first NMOS transistor. Theprecharge transistor can be an NMOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings in which like reference characters refer tothe same parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention.

[0038]FIG. 1 is a block diagram of a semiconductor memory device havinga conventional output driver.

[0039]FIG. 2 is a waveform diagram of an output signal of the outputdriver of FIG. 1.

[0040]FIG. 3 is a timing diagram showing the relationship between areference clock signal of the rambus DRAM and data.

[0041]FIG. 4 is a circuit diagram of an output driver circuit of therambus DRAM.

[0042]FIG. 5 is a waveform diagram for illustrating a read operation ofthe output driver circuit of FIG. 4.

[0043]FIG. 6 is a timing diagram showing a delay for data due to a risein a voltage of a connection node of FIG. 4.

[0044]FIG. 7 is a block diagram of a semiconductor memory device havingan output driver according to a first embodiment of the presentinvention.

[0045]FIG. 8 is a block diagram of a semiconductor memory device havingan output driver according to a second embodiment of the presentinvention.

[0046]FIG. 9 is a circuit diagram of a semiconductor memory deviceaccording to a third embodiment of the present invention.

[0047]FIG. 10 is a waveform diagram for explaining a read operation ofthe output driver of FIG. 9.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0048] The present invention now will be described more fully withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. In the drawings, the shapes of elements areexaggerated for clarity.

[0049]FIG. 7 is a block diagram of a semiconductor memory device havingan output driver according to a first embodiment of the presentinvention. Referring to FIG. 7, a semiconductor memory device 700according to a first embodiment of the present invention includes anoutput driver 710 in which a first NMOS transistor N1 and a second NMOStransistor N2 are connected in series, the drain of the first NMOStransistor N1 is connected to an output pad DQ, and the source of thesecond NMOS transistor N2 is connected to a ground voltage VSS. A firstinternal voltage VGATE is applied to the gate of the first NMOStransistor N1, and a second internal voltage VINT is applied to the gateof the second NMOS transistor N2. The second internal voltage VINT islower than an external supply voltage.

[0050] The second internal voltage VINT is generated from an internalvoltage generating circuit of the semiconductor memory device 700 or isexternally applied directly from outside the semiconductor memory device700. The voltage level of the second internal voltage VINT may bedifferent from the level of an operating voltage of the semiconductormemory device 700.

[0051] Hereinafter, operation of the semiconductor memory deviceaccording to the first embodiment of the present invention will bedescribed with reference to FIG. 7.

[0052] In the semiconductor memory device 700 of FIG. 7, a first drivingcircuit 720 which generates a first internal voltage VGATE and a seconddriving circuit 730 which generates a second internal voltage VINT areshown beside the output driver 710.

[0053] When data DATA is read, the first driving circuit 720 generatesthe first internal voltage VGATE for driving the first NMOS transistorN1 of the output driver 710. The second driving circuit 730 receives aninternal supply voltage IVCC and data DATA sensed and outputted from aDRAM cell (not shown) and generates the second internal voltage VINThaving the same logic level as the logic level of the data DATA.

[0054] If the data DATA has a high frequency, such as data in a rambusDRAM, the second internal voltage VINT output from the second drivingcircuit 730 is not capable of performing a full swing between the highlevel and the low level. This is particularly the case when the logiclevel of the outputted data DATA changes between the high level and thelow level because the time necessary for the rise of the data DATA islong in comparison to the high frequency of the data DATA.

[0055] Accordingly, in the device of the invention, the second internalvoltage VINT is generated at a lower level than the conventional levelof the external supply voltage. Then, the time necessary for swingingthe second internal voltage VINT from the low level to the high level isreduced in proportion to the fallen voltage level, and thus a full swingcan be performed.

[0056] If the voltage level of the second internal voltage VINT islowered, the waveform of the gate Q of the second NMOS transistor N2 hasa spherical shape as shown in FIG. 2A. Then, the waveform output fromthe output pad DQ may be delayed.

[0057] The voltage level of the second internal voltage VINT may begenerated from the internal voltage generating circuit, such as thesecond driving circuit 730 shown in FIG. 7, or may be applied directlyfrom outside the chip.

[0058] In addition, the voltage level of the second internal voltageVINT may be different from the level of the operating voltage levelwhich operates other circuits of the semiconductor memory device 700.

[0059]FIG. 8 is a block diagram of a semiconductor memory device havingan output driver according to a second embodiment of the presentinvention. Referring to FIG. 8, a semiconductor memory device 800according to the second embodiment of the present invention includes anoutput driver 810 in which a first NMOS transistor N1 and a second NMOStransistor N2 are connected in series, the drain of the first NMOStransistor N1 is connected to an output pad DQ, and the source of thesecond NMOS transistor N2 is connected to a ground voltage VSS1. Thesemiconductor memory device 800 also includes a first driving circuit820 and a second driving circuit 830 which applies a driving voltageVINT to the gate of the second NMOS transistor N2 in response to aninternal supply voltage IVCC. A ground voltage level VSS2 of the seconddriving circuit 830 is higher than the ground voltage level VSS1 towhich the source of the second NMOS transistor N2 is connected.

[0060] The voltage level of the driving voltage VINT may be differentfrom the level of the operating voltage of the semiconductor memorydevice 800. The voltage level of the driving voltage VINT may be lowerthan that of the external supply voltage.

[0061] Hereinafter, the operation of the semiconductor memory deviceaccording to the second embodiment will be described with reference toFIG. 8. When the data DATA is read, the first NMOS transistor N1 isturned on. When a high level of the driving voltage VINT is applied tothe gate Q of the second NMOS transistor N2, the second NMOS transistorN2 is turned on, and thus the output signal is outputted at a low level.

[0062] The second driving circuit 830 applies the driving voltage VINTto the gate Q of the second NMOS transistor N2 in response to the dataDATA and the internal supply voltage IVCC. The function of the seconddriving circuit 830 is the same as that of the second driving circuit730 of FIG. 7, and therefore detailed descriptions thereof will not berepeated here.

[0063] The first driving circuit 820 generates a gate voltage VGATE froma reference voltage REFV, for driving the first NMOS transistor N1 ofthe output driver 810. The functions of the first driving circuit 820are the same as those of the first driving circuit 720 of FIG. 7, andthus detailed descriptions thereof will not be repeated here.

[0064] In the first embodiment of FIG. 7, the voltage level of the highlevel of the second internal voltage VINT, which is applied to the gateQ of the second NMOS transistor N2 of the output driver 710, is loweredso as to perform a full swing from the low level to the high level.

[0065] In the second embodiment illustrated in FIG. 8, the voltage levelof the low level of the driving voltage VINT, which is applied to thegate Q of the second NMOS transistor N2 of the output driver 810, isenhanced. Here, the voltage level of the ground voltage VSS2 of thesecond driving circuit 830 is enhanced to be higher than the voltagelevel of the ground voltage VSS1 of the output driver 810, and thus thevoltage level of the low level of the driving level VINT is enhancedaccordingly. The time necessary for the driving voltage VINT to performa swing from the low level to the high level is decreased by theenhanced voltage, and thus a full swing may be performed.

[0066] The voltage level of the driving level VINT may be different fromthat of the operating voltage level which operates other circuits of thesemiconductor memory device 800. In addition, the voltage level of thedriving voltage VINT may be lower than the external supply voltage andachieves results similar to those shown in the first embodiment of FIG.7.

[0067]FIG. 9 is a circuit diagram of a semiconductor memory deviceaccording to a third embodiment of the present invention. FIG. 10 is awaveform diagram for illustrating a read operation of the output driverof FIG. 9.

[0068] Referring to FIG. 9, a semiconductor memory device 900 accordingto the third embodiment of the present invention includes an outputdriver 910 in which a first NMOS transistor N1 and a second NMOStransistor N2 are connected in series, the drain of the first NMOStransistor N1 is connected to an output pad DQ, and the source of thesecond NMOS transistor N2 is connected to a ground voltage VSS. Thesemiconductor device 900 also includes a precharge transistor 920, inwhich the source is connected to a connection node A of the first NMOStransistor N1 and the second NMOS transistor N2 and the drain isconnected to a supply voltage VDD. A voltage compensating circuit 930between the connection node A of the output driver 910 and the gate ofthe precharge transistor 920 lowers the rise in the voltage level of theconnection node A due to the rise in the voltage level of the gate ofthe first NMOS transistor N1.

[0069] The voltage compensating circuit 930 may be a capacitor which isconnected between the gate and the source of the precharge transistor920. The capacitor has the same capacitance as a coupling capacitorbetween the gate and the source of the first NMOS transistor N1. Theprecharge transistor 920 may be an NMOS transistor.

[0070] Hereinafter, the operation of the semiconductor memory deviceaccording to the third embodiment of the present invention will bedescribed with reference to FIG. 9. When the data is read, the voltagelevel of the second gate voltage PVGATE is lowered from the high levelto the low level, contrary to the first gate voltage VGATE which isapplied to the first NMOS transistor N1.

[0071] The voltage compensating circuit 930 lowers the voltage level ofthe connection node A using a capacitor. The capacitor has the samecapacitance as the coupling capacitor between the gate and the source ofthe first NMOS transistor N1.

[0072] When the data is read, the gate of the first NMOS transistor N1is charged by the first gate voltage VGATE, and the gate of theprecharge transistor 920 is discharged by the second gate voltagePVGATE, at the same time.

[0073] Therefore, the voltage of the connection node A due to the gateof the first NMOS transistor N1 to junction overlap is raised and thevoltage of the connection node A is lowered by the voltage compensatingcircuit 930 at the same time, and therefore, the rise of the voltagelevel of the connection node A compensates for the fall of the voltagelevel of the connection node A and vice versa. Therefore, the voltagelevel of the connection node A experiences little change, which isillustrated in FIG. 10.

[0074] When the high level of data is output to the output pad DQ, thedecrease of TQMAX by 13 ps may be compensated by the voltagecompensating circuit 930.

[0075] As described above, a semiconductor memory device according tothe present invention can output data at a high frequency without anydistortion, thus ensuring superior output characteristics and greatlyimproved timing margin.

[0076] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention as defined by the appended claims and equivalents.

What is claimed is:
 1. A semiconductor memory device having an outputdriver in which a first NMOS transistor and a second NMOS transistor areconnected in series, a drain of the first NMOS transistor is connectedto an output pad, and the source of the second NMOS transistor isconnected to a ground voltage, wherein: a first internal voltage isapplied to the gate of the first NMOS transistor and a second internalvoltage is applied to the gate of the second NMOS transistor; and avoltage level of the second internal voltage is lower than the voltagelevel of an external supply voltage.
 2. The semiconductor memory deviceof claim 1, wherein the second internal voltage is generated directlyfrom an internal voltage generating circuit of the semiconductor memorydevice or is externally applied.
 3. The semiconductor memory device ofclaim 1, wherein the voltage level of the second internal voltage isdifferent from the level of an operating voltage of the semiconductormemory device.
 4. A semiconductor memory device having an output driverin which a first NMOS transistor and a second NMOS transistor areconnected in series, the drain of the first NMOS transistor is connectedto an output pad, and the source of the second NMOS transistor isconnected to a ground voltage, having a driving circuit which applies adriving voltage to the gate of the second NMOS transistor in response todata, and an internal supply voltage, wherein a ground voltage level ofthe driving circuit is higher than the voltage level of the groundvoltage to which the source of the second NMOS transistor is connected.5. The semiconductor memory device of claim 4, wherein the voltage levelof the driving voltage is different from the level of an operatingvoltage of the semiconductor memory device.
 6. The semiconductor memorydevice of claim 4, wherein the voltage level of the driving voltage islower than the voltage level of an external supply voltage.
 7. Asemiconductor memory device having an output driver in which a firstNMOS tansistor and a second NMOS transistor are connected in series, thedrain of the first NMOS transistor is connected to an output pad, andthe source of the second NMOS transistor is connected to a groundvoltage, and having a precharge transistor of which the source isconnected to a connection node of the first NMOS transistor and thesecond NMOS transistor and of which drain is connected to a supplyvoltage, wherein the precharge transistor includes a voltagecompensating circuit for lowering the rise in the voltage level of theconnection node due to the rise in the voltage level of the gate of thefirst NMOS transistor.
 8. The semiconductor memory device of claim 7,wherein the voltage compensating circuit comprises a capacitor which isconnected between the gate and the source of the precharge transistor.9. The semiconductor memory device of claim 8, wherein the capacitor hasthe same capacitance as a coupling capacitor between the gate and thesource of the first NMOS transistor.
 10. The semiconductor memory deviceof claim 7, wherein the precharge transistor is an NMOS transistor.